A tristate bus driver (also called a tristate buffer), when enabled by an enable signal applied to its enable terminal, outputs a logical 1 or 0 signal in response a logical 1 or 0 signal applied to its input. When the tristate bus driver is not enabled by an enable signal, its output is an open circuit.
Various types of integrated circuits (IC) incorporate a plurality of tristate bus drivers connected to a common bus, where the tristate bus drivers are selectively enabled. The tristate bus drivers are typically selectively enabled so that the common bus will only be driven to a full logical 1 or a full logical 0 by a single driver.
One means of providing such driver selection is with the use of a state machine whose outputs are connected to the enable terminals of the various tristate bus drivers. In normal operation, the state machine would be programmed to generate a clocked pattern of enable signals to enable the various tristate bus drivers individually or in any sequence.
Typically, for testing the IC, a model of the IC circuitry is created using a netlist. This model is then used in conjunction with a customized automatic test generation (ATG) computer program to generate test stimuli and responses. When testing the IC, the test stimuli are applied to selected input nodes of the IC. The resulting output signals at selected output nodes of the IC are then compared with the predicted responses to determine whether the IC is operating properly.
When the IC incorporates tristate bus drivers connected to a common bus, such as tristate bus drivers 10-13 in FIG. 1a connected to common bus 15, the ATG model models these tristate bus drivers as AND gates connected to a single OR gate, such as AND gates 20-23 connected to OR gate 24 in FIG. 1b.
D-type latch 26 and modeled D-type latch 27 are shown connected to bus 15 and OR gate 24, respectively, as representative of a device receiving a signal from bus 15 or OR gate 24.
As seen from a comparison of FIGS. 1a and 1b, the ATG model models each tristate bus driver as an AND gate having two inputs, where one input receives the information signal and the other input receives the enable signal. Thus, if the enable signal is a logical 1, the output of the AND gate follows the information signal.
OR gate 24 provides a model of the common connection of the outputs of tristate bus drivers 10-13, wherein if any of the outputs of AND gates 20-23 is a logical 1, the output of OR gate 24 will be a logical 1. Conversely, if none of the outputs of AND gates 20-23 is a logical 1, the output of OR gate 24 will be a logical 0.
However, this model of FIG. 1b does not accurately reflect the level on bus 15 if two or more bus drivers 10-13 are concurrently enabled, either intentionally or inadvertently, and the outputs of the enabled drivers include both logical 1's and logical 0's. In such a case, the level of bus 15 will neither be fully a logical 1 nor a logical 0 level, while the modeled level at the output of OR gate 24 will be an ideal logical 1. Further, if none of the drivers 10-13 are enabled, bus 15 will float. This state is also not accurately modeled by OR gate 24, whose output may only be an ideal logical 1 or logical 0.
Due to such an anomaly between the operation of the actual circuitry of FIG. 1a and the ATG model of FIG. 1b, means have been incorporated in prior art IC's to cause one and only one of the actual tristate bus drivers to be enabled at a time during ATG testing. Hence, in such a case, the ATG model accurately reflects the actual tristate bus drivers 10-13, since only a full logical 1 or logical 0 can now appear on bus 15.
One such prior art means to enable only one tristate bus driver at a time is shown in FIG. 2. In FIG. 2, central decoder 30 is inserted between tristate bus drivers 10-13 and state machine 34 to only allow one of drivers 10-13 to be enabled at any one time. Since the ATG program typically is not designed to understand the IC's permissible operation modes, without decoder 30 the ATG program could undesirably generate test signals which would cause state machine 34 to concurrently enable two or more of drivers 10-13.
The disadvantages to this prior art approach shown in FIG. 2 include: (1) the additional circuit size and propagation delay incurred by routing all tristate enable signals from state machine 34 into a central decoder 30 and routing the decoder 30 outputs to the enable terminals of tristate bus drivers 10-13; (2) significant delays from the charging and discharging of the parasitic input capacitance of the decoder 30, especially if decoder 30 has a large fan-in; (3) the added complexity in designing the ATG methodology to model decoder 30; and (4) if state machine 34 is designed to provide already decoded enable signals, then application of the ATG methodology requires additional encoding and decoding of these state machine signals to ensure only one buffer is enabled at a time.
Thus, what is desirable is a circuit containing tristate bus drivers which simplifies ATG methodologies and which does not suffer from the above-described drawbacks incurred when using a central decoder or similar means to prevent simultaneous enablement of opposing bus drivers.